First off, if you write dates in a format where the month comes before the day, then today for you is Pi Day (3/14 -> 3.14). Happy Pi Day! However, the point of this log is not to talk about Pi Day, but rather to talk about some simple CPU design.
Though I had planned to work on my Lisp interpreter a lot this week, I have ended up spending the better part of the past 5 or so days writing a simple CPU in Verilog that runs on my FPGA. After having rewritten the instruction set and architecture about three times, and having spent a fair amount of time sitting and thinking about what design decisions to make, I can safely say that I will definitely still be changing some of the instructions in the very near future. The CPU is "16-bit," meaning it uses a 16-bit address bus, has 16-bit fixed-length instructions, and uses all 16-bit registers. After getting tired of hand-writing hexadecimal machine code for testing and simulation of the processor, I also ended up writing a very simple (and bad) assembler in Python that at least lets me use named opcodes, registers, and labels (for branching).
I eventually hope to release the code for the processor, but it will need to be cleaned up a little bit first, and the Git history will need to be edited some. However, I would still like to provide a listing of the software I used to do this project. The iCE40-HX8K that I used is somewhat unique, in that there exists an entirely open-source toolchain for programming it. Said toolchain consists of the Yosys Open SYnthesis Suite for compiling and synthesizing your Verilog code, Arachne-pnr for placing and routing, and Project IceStorm for crafting a bitstream to feed to the FPGA. With these tools combined into a Makefile, programming the iCE40 becomes very easy (assuming you know how to use Verilog; there are a fair number of good examples out there to get started with).
One other major piece of software that I used in creating my CPU was the Icarus Verilog compiler, along with its vvp runtime engine and the GTKWave wave viewer. Together, this software stack allowed me to fully simulate the behavior of my CPU without having to synthesize it (a much more time-intensive process than simply compiling and simulating). I actually simulated a large part of the processor long before trying to run it on actual hardware.
As I mentioned earlier, I do want to release my code for this project, but there is some clean-up that needs to be done first; "stay tuned" is the best you get at the moment.